1. Field of the Invention
The present invention relates to a semiconductor device and a semiconductor device manufacturing method, and, more particularly to a semiconductor device and a semiconductor device manufacturing method suitable for application to a semiconductor device having silicon germanium layers mounted together on a silicon substrate.
2. Description of the Related Art
In some manufacturing processes of semiconductor devices such as a bulk complementary metal-oxide semiconductor (CMOS), driving force of a field-effect transistor is improved by forming an active region in a silicon germanium layer by adding germanium to a silicon substrate (see Study on High Performance (110) PFETs with Embedded SiGe, Okamoto, S.; Miyashita, K.; Yasutake, N.; Okada, T.; Itokawa, H.; Mizushima, I.; Azuma, A; Yoshimura, H.; Nakayama, T.; Electron Devices Meeting, 2007. IEDM 2007. IEEE International, 10-12 Dec. 2007, Page(s): 277-280).
However, when a silicon germanium layer is formed on a silicon substrate, a breakdown voltage of a PN junction decreases, a junction leak current increases, or a forward diffusion current remarkably increases. When a silicon germanium layer is formed in source/drain regions by an epitaxial growth, a PN junction is formed at a position very shallow from an original silicon surface before performing the epitaxial growth. Therefore, a junction leak increases. Consequently, although the method of forming a silicon germanium layer on a silicon substrate is useful to increase speed of a field-effect transistor, this method has a problem of decreasing capacity of an electrostatic protection element, and increasing a leak current during a normal operation, for the electrostatic protection element that includes a PN junction diode and the like.
Furthermore, the method of using a silicon germanium layer particularly contributes to increase driving force of a P-channel field-effect transistor. Therefore, when a load transistor of a static random access memory (SRAM) includes a P-channel field-effect transistor, there are the following problems. An operation of pulling down a bit line at a data writing time is interrupted by the load transistor. As a result, a write margin of the SRAM decreases, and a junction leak of a bit cell unit of the SRAM also increases.